Automatic test equipment (ATE) manufacturers employ pin driver circuits for controllably applying respective high and low voltages to an output terminal to which a device under test is coupled. FIG. 1 schematically illustrates the basic components of a commercially available pin driver circuit employed in an ATE system manufactured by Fairchild Corporation, in which first and second diode bridge circuits 11 and 13 are respectively coupled between a high voltage VH input terminal 15 and an output terminal 20, on the one hand, and between a low voltage VL input terminal 17 and the output terminal 20, on the other hand. The capacitance associated with output terminal 20 is shown in the figure as a capacitive load 21. Switchably coupled to opposite ends of each diode bridge are respective current sources 22 and 24.
When it is desired to couple the high voltage input VH at terminal 15 to output terminal 20, controlled switching elements 27, 28 are operated to steer each of current sources 22, 24 to diode bridge 11, while diode bridge 13 for the low voltage VL is electrically isolated from the current sources. The high voltage VH at terminal 15 is thus coupled to output terminal 20 through diode bridge 11. Conversely, when it is desired to couple the low voltage input VL at terminal 17 to output terminal 20, controlled switching elements 27, 28 are operated to steer each of current sources 22, 24 to diode bridge 13, while diode bridge 11 is electrically isolated from the current sources. The low voltage VL at terminal 15 is thus coupled to output terminal 20 through diode bridge 13.
Because it can be expected that semiconductor processing of the circuit design will match the characteristics of the diodes of the respective upper portion and lower portion of a bridge, the circuit shown in FIG. 1 will enjoy low offset voltage between the voltage input terminals and output terminal 20. However, because of the inherent capacitance of the diodes, there is a substantial switching delay, and the uneven biasing of the diodes during a transition from low to high (or high to low) will cause current from the source to which the diodes are connected to be apportioned through each diode, which necessitates that buffer circuits be coupled to the input voltage terminals to absorb the current component apportioned to the input terminal.
In the case of diodes 11-1 and 11-2 of the upper portion of diode bridge 11, for example, when output terminal 20 is to transition from a low voltage state (e.g. VL=0) to a high voltage state (e.g. VH=1), diode 11-1 is initially reverse-biased (input terminal 15 is at VH=1), whereas diode 11-2 is forward biased (output terminal 20 is initially at VL=0). Thus, at the start of a low to high transition, the entirety of the current flow path is through diode 11-2 to output terminal 20. As current from source 22 continues to flow and charge capacitive load 21, the forward bias of diode 11-2 begins to decrease, so that the current from source 22 begins to split between diodes 11-1 and 11-2, whereby part of the current will flow to output terminal 20 and part of the current will flow into terminal 15. Because of the inherent capacitance of diodes 11- 1 and 11-2, there is an increase in the switching delay in bringing output terminal 20 to the input voltage (e.g. VH=1). Moreover, in order to accommodate the flow of current through the diodes that are connected to the voltage input terminals (e.g. through diode 11-1 to VH voltage input terminal 15), it is necessary to provide respective output buffers for each of voltage input terminals 15 and 17 capable of absorbing substantial current (e.g. milliamps). Thus, the pin driver of FIG. 1 suffers from slow switching speed and the need for additional buffer circuitry components.